TY - BOOK AU - Grasser, Tibor AU - Filipovic, Lado AB - What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications. DO - 10.3390/books978-3-03921-011-4 ID - OAPEN ID: 33701 KW - MOSFET KW - n/a KW - total ionizing dose (TID) KW - low power consumption KW - process simulation KW - two-dimensional material KW - negative-capacitance KW - power consumption KW - technology computer aided design (TCAD) KW - thin-film transistors (TFTs) KW - band-to-band tunneling (BTBT) KW - nanowires KW - inversion channel KW - metal oxide semiconductor field effect transistor (MOSFET) KW - spike-timing-dependent plasticity (STDP) KW - field effect transistor KW - segregation KW - systematic variations KW - Sentaurus TCAD KW - indium selenide KW - nanosheets KW - technology computer-aided design (TCAD) KW - high-? dielectric KW - subthreshold bias range KW - statistical variations KW - fin field effect transistor (FinFET) KW - compact models KW - non-equilibrium Green’s function KW - etching simulation KW - highly miniaturized transistor structure KW - compact model KW - silicon nanowire KW - surface potential KW - Silicon-Germanium source/drain (SiGe S/D) KW - nanowire KW - plasma-aided molecular beam epitaxy (MBE) KW - phonon scattering KW - mobility KW - silicon-on-insulator KW - drain engineered KW - device simulation KW - variability KW - semi-floating gate KW - synaptic transistor KW - neuromorphic system KW - theoretical model KW - CMOS KW - ferroelectrics KW - tunnel field-effect transistor (TFET) KW - SiGe KW - metal gate granularity KW - buried channel KW - ON-state KW - bulk NMOS devices KW - ambipolar KW - piezoelectrics KW - tunnel field effect transistor (TFET) KW - FinFETs KW - polarization KW - field-effect transistor KW - line edge roughness KW - random discrete dopants KW - radiation hardened by design (RHBD) KW - low energy KW - flux calculation KW - doping incorporation KW - low voltage KW - topography simulation KW - MOS devices KW - low-frequency noise KW - high-k KW - layout KW - level set KW - process variations KW - subthreshold KW - metal gate stack KW - electrostatic discharge (ESD) L1 - https://mdpi.com/books/pdfview/book/1370 LA - English LK - https://directory.doabooks.org/handle/20.500.12854/53550 PB - MDPI - Multidisciplinary Digital Publishing Institute PY - 2019 SN - 9783039210107 SN - 9783039210114 TI - Miniaturized Transistorsnull ER -